1. Field of the Invention
The present invention relates to testing distributed logic and analog circuits, such as, circuitry in phase interpolators and delay locked loops (DLL).
2. Description of the Related Art
As the technology for manufacturing integrated circuits advances, more logic functions are included in a single integrated circuit device or a system on a chip (SoC). Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as a manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
However, as the complexity of the ICs and SoCs increase, so does the cost and complexity of verifying and electrically testing the individual IC or multiple ICs in a system for a SoC. Testing and manufacturing costs and design complexity increase dramatically not only because of the increasing number of functional pins on the integrated devices and SoC, but because of the increasing complexity of both the analog and digital circuitry supporting each pin.
Likewise, Input/Output (I/O) circuitry may be self tested during various phases of circuit test from wafer sort to platform validation. At various states of test, IO pads may not be contacted by a tester. Nonetheless, test equipment needs to detect manufacturing defects. Typically, additional circuitry or sensing or customized testing patterns are needed.